SiFive and Open-Silicon Join Hands to Host RISC-V Tech Symposiums in India
Business Wire India
SiFive and Open-Silicon, two global giants of the semiconductor industry started their six-city RISC-V Tech Symposium Tour from Hyderabad. The Tech Symposium was attended by industry leaders and dignitaries such as Shri MM Pallam Raju, Former Union Minister, Government of India; Mr. Keshav Dattatreya Nayak, Scientist and Former Director General DRDO; Manu Verma, Sr. Manager, Product Marketing, Microsemi Corporation; Varma Konala, Business Head, Smart Devices, Intel Corporation; Kunal Ghosh, Director & Co-Founder, VSD and Anagha Ghosh, Business Head & Co-Founder, VLSI System Design along with Dr. Krste Asanovic, Chairman of RISC-V Foundation and Mr. Sunil Shenoy, VP of Hardware Engineering, SiFive.
RISC-V, an open instruction set architecture has shaken up the technology world and is rapidly increasing its ecosystem. It is being preferred by leading system, chip design organizations, several start-ups and governments around the world. The tech symposium in Hyderabad provided a platform for industry experts, students and engineers to share their thoughts on the future of RISC-V, its impact on defense sector, state of India’s semiconductor industry, hardware startups, embedded systems, IoT among others. The event enabled its diverse audience on the nuances of standardization of RISC-V ISA for all computing devices. The speakers also provided impetus on the operational efficiency required in the Military and Defense sector and the need to meet this demand through advancing custom system-on-chip (SoC) technology.
Design Idea Contest 2018
At the event, SiFive also announced first of its kind Design Contest in India. The Design Contest aims to enable some of the most underutilized ideas from academia, students, research institutions and open source communities. SiFive will collaborate with the best ideas and provide the winners’ access to custom CPU IP, design support, and help in delivering working samples for the chip. The contest will run from 21st August till 30th November 2018.
“The fact that the government of India has officially adopted RISC-V as the national ISA, underscores the power of the architecture and its capacity to enable innovative commercial and military applications,” said Krste Asanovic, Co-Founder and Chief Architect of SiFive. “We are honored that MM Pallam Raju, the Former Union Cabinet Minister of HRD for the government of India, and Keshav Nayak, Distinguished Scientist and Former Director General, Defense Research and Development Organization, joined us at the symposium in Hyderabad and shared their views on the robust semiconductor ecosystem in India and the role that RISC-V plays for defense electronics,” added Krste Asanovic.